VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture Notes - Verilog, Sequential Circuits, And Gate

• School: Indian Institute of Technology - IIT Kharagpur
• Department: Engineering
• Course: VERILOG SIMULATIONS (DIGITAL ELECTRONICS)

Document Summary

It is a language using which a designer can specify the behaviour or structure of a specific hardware. Understand difference between behaviour and structural design styles. Learn to write test benches and analyse simulation results. In verilog the basic unit of hardware is called a module(like a function definition in c). A module cannot contain definition of other modules. A module can however be instantiated within another module. Instantiation allows the creation of a hierarchy in verilog description. Syntax :- module module_name (list_of_ports) input/output declarations local net declarations. Parallel statements mean they are executed simultaneously since they are circuits. Unlike a c program they are not executed one line after the other. In the sample above program, we define a module of and function. The port list is f, x, and y. Well, if you just mention x, y and f, it will mean, these are all one bit variables. & means and function need not be an and gate.