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Find Class Notes for Engineering at Indian Institute of Technology - IIT Kharagpur

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Top Class Notes for Engineering at Indian Institute of Technology - IIT Kharagpur

Out of 14 Class NotesAbout Indian Institute of Technology - IIT Kharagpur

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ME21101 Lecture : Fluid Mechanics
sarthak
4310
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture 3: Divisibility_Check : The aim is to design a circuit that takes 8 bit binary input and gives output "1" if the aggregate binary input is divisible by n where n is a positive integer.
guevara0614
45
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture 2: Barrel_Shifter_verilog : Implement the structural model of barrel shifter in verilog that performs logical shift left or shift right based on the control input
guevara0614
710
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture Notes - Combinational Logic
guevara0614
77
IM21001 Lecture 1: 01 EECA
aksingh
2812
IM21001 Lecture : 02 EECA
aksingh
5210

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Class Notes contributors from Engineering at Indian Institute of Technology - IIT Kharagpur

3 Class Notes contributors
aksingh
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guevara0614
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sarthak
sarthak
2 uploads
aksingh
aksingh
7 uploads
guevara0614
guevara0614
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sarthak
sarthak
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Engineering courses at Indian Institute of Technology - IIT Kharagpur

4 courses are found from Engineering department of Indian Institute of Technology - IIT Kharagpur
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IM21001
7 Class Notes
ME21101
1 Class Note
ME21201
1 Class Note
VERILOG SIMULATIONS (DIGITAL ELECTRONICS)
5 Class Notes

Recent Class Notes from Engineering at Indian Institute of Technology - IIT Kharagpur

Out of 14 Class Notes

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ME21101 Lecture : Fluid Mechanics
sarthak
4310
ME21201 Lecture : Mechanics Of Solids
sarthak
3712
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture Notes - Verilog, Sequential Circuits, And Gate
guevara0614
911
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture 4: Demultiplexer and 8bitALU : The report shows the implementation of 1x8 demultiplexer and 8bit ALU using data flow modelling in verilog.
guevara0614
67
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture 3: Divisibility_Check : The aim is to design a circuit that takes 8 bit binary input and gives output "1" if the aggregate binary input is divisible by n where n is a positive integer.
guevara0614
45
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture 2: Barrel_Shifter_verilog : Implement the structural model of barrel shifter in verilog that performs logical shift left or shift right based on the control input
guevara0614
710
VERILOG SIMULATIONS (DIGITAL ELECTRONICS) Lecture Notes - Combinational Logic
guevara0614
77
IM21001 Lecture : 05 EECA
aksingh
2214
IM21001 Lecture 1: 01 EECA
aksingh
2812
IM21001 Lecture : 02 EECA
aksingh
5210
IM21001 Lecture : 06 EECA
aksingh
1915
IM21001 Lecture : 03 EECA
aksingh
2312

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