SYSC 2320 Study Guide - Quiz Guide: Computer Engineering
13 Jan 2021
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In this homework we will focus on the basic processor in figure 1. For speci c operations, refer to the operation table in the lecture slides: suppose that fetching and pc incrementing are implemented sequentially, rather than in parallel as in class. That is, suppose that fetching takes place rst, followed by pc incrementing. Data bus: in the previous table, include columns for the decode, e0, e1 and e2 states, design a rom implementation for the fsm table obtained in the previous problems. You will need to connect a state register. You must determine the active clock edge and you must determine the size of the rom needed. 1: in this problem, we will revert to the standard (parallel) construction described in class. Using the following register and memory values, determine the contents of t1, t2, mar, mdr and ir in each state, i. e. , f0, f1, f2, decode (f3), e0, e1 and e2.
