SYSC 2320 Study Guide - Quiz Guide: Machine Code, And Gate, Clock

• School: Carleton University
• Department: Systems and Computer Engineering
• Course: SYSC 2320
• Professor: Gohary

Document Summary

Do you see why state-merging is feasible: solution of problem #2. 0000 xxxx xxxx: for the (ine cient) machine considered in problems # 1 and # 2, we have 10 states. The implementa- tion depends on number of operands, either 0 (nop), 2 (not and ry) or 3 (all the rest). The decode state will branch into 3 states, state f0 for nop, state e1 for not and ry, and state e0 for all the rest. Using an implementation similar to the one used in the lab. Rom will output state f0 (for nop) or state e1 (for not and ry) or state e0 (for all the rest). Since the number of states is greater than 8 and less than 16, we need 4 bits to represent the states. Rom with the following binary addresses: 00 for nop, 01 for not and ry, and 10 for all the rest.