ECE 120 Lecture 20: lecture_20

• School: University of Illinois
• Department: Electrical and Computer Engineering
• Course: ECE 120
• Professor: Kindratenko Volodymyr

Document Summary

We can transform this bit-sliced design to a serial sequential design: with a single copy of the bit slice logic, m + q flip-flops, and, m gates. For the 1st cycle, we apply f=1, and the initial values are passed into the bit slice. Bit-sliced implementation: to add two n-bit numbers a = an-1an-2 a1a0 and b = bn-1bn-2 b1b0, we arrange n fas as shown below. The low-order c0 must be set to 0 and the output is the n-bit sum sn-1 s1s0 and a carry out bit cn: such design is called ripple carry adder because carry bits ripple (propagate) through the network. In all other cycles, f = 0, and the nor gates set cin = q. The above implementation is a mealy machine: the output depends on the present state and the external input. A single bit from each of the two numbers being compared.