ECE 120 Lecture Notes - Lecture 29: Operand, Danube, Bitwise Operation

• School: University of Illinois
• Department: Electrical and Computer Engineering
• Course: ECE 120
• Professor: Kindratenko Volodymyr

Document Summary

Operation: bitwise complement of the value from the source register (sr) is stored in the destination register (dr: dr not(sr, setcc. Datapath relevant to the execution of this instruction: example: 1001 011 101 111111; not r3, r5. Operation: values from two source registers (sr1 and sr2) are added together (using 2"s complement addition) and the resulting value is stored in the destination register (dr: dr sr1 + sr2, setcc. Datapath relevant to the execution of this instruction: example: 0001 001 010 0 00 110; add r1, r2, r6. 1opcode001111111destination registersource registerunused bitsnot151413121110987654321001000000111001011011111100011010r0r1r2r3r4r5r6r716alu16notn=0z=0p=10opcode001000destination registersource register 1unused bitsadd1514131211109876543210source register 2addressing modeece 120. Datapath relevant to the execution of this instruction: example: 0001 001 100 1 11110; add r1, r4, #-2. 000000000001001000000000000000110000000000001111r0r1r2r3r4r5r6r716alu16addn=0z=0p=10opcode0011destination registersource register 1add15141312111098765432105-bit 2"s complement numberaddressing mode00000000000001000000000000000110r0r1r2r3r4r5r6r716alu16addn=0z=0p=1160001001100111110ir165dr3srsext3ir[5]ece 120. November 4, 2015 imm5 field is 5-bit long in 2"s complement, it is sufficient to represent numbers in the interval from -24 to 24-1 (-16 15)