EE 3755 Midterm: EE 3755 LSU 2012fMidterm sol

• School: LSU
• Department: Electrical Engineering
• Course: EE 3755
• Professor: All

Document Summary

Problem 7 (15 pts) (14 pts) (14 pts) (14 pts) (18 pts) (11 pts) (14 pts) // solution assign x = !a && b || c; assign y = !a && b && c; endmodule. Problem 2: [14 pts] appearing below is a verilog description of a two-level adder used in homework 2. module adder_r4_c3(sum,a,b); input [11:0] wire [2:0] a, b; P, g, carry, co; output [12:0] sum; carry[0]); ripple_4_block ad0(sum[3:0], ripple_4_block ad1(sum[7:4], carry[1]); ripple_4_block ad2(sum[11:8], co[2], a[11:8], b[11:8], carry[2]); Co[1], a[7:4], b[3:0], b[7:4], gen_prop_4 gp0(g[0], p[0], a[3:0], gen_prop_4 gp1(g[1], p[1], a[7:4], gen_prop_4 gp2(g[2], p[2], a[11:8], b[11:8]); b[3:0]); b[7:4]); assign assign assign assign endmodule carry[0] = 1"b0; carry[1] = g[0]; carry[2] = g[0] & p[1] | g[1]; sum[12] = g[0] & p[1] & p[2] | g[1] & p[2] | g[2]; (a) suppose that the input to the adder were a=0x123 and b=0xabc. For the rst two parts above, pay attention to the bit positions.