EE 3755 Midterm: EE 3755 LSU 2001fMidterm sol
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Problem 6 (16 pts) (16 pts) (20 pts) (16 pts) (16 pts) (16 pts) Problem 1: add verilog code to the 32-bit carry-lookahead adder module below for the carry[5] wire. Use the generate and propagate signals. (16 pts) module cla_32(sum,a,b); input [31:0] a, b; output [32:0] sum; wire [31:0] g, p, carry; // code for other cla_slices omitted. cla_slice s5(sum[5],g[5],p[5],a[5],b[5],carry[5]); Problem 2: complete the module below so that 32-bit output sum is the sum of its 32-bit inputs, a and b. If input s is 1 then a and b are signed integers, otherwise they are unsigned integers. Output overflow should be set to 1 if the sum over ows. The solution can (and should) use the addition operator. (16 pts) Problem 3: the module below examines a bit sequence one bit per clock cycle, as did the module in homework 2 problem 2.
