ECE327 Midterm: ECE 327 University of Waterloo 2013 Term 1 Midterm Solution

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

All requests for re-marks must be submitted in writing to mark aagaard before 8:30am on monday march 11. Ex- ams that are submitted for re-marking will be veri ed against this set. Q1 (20 marks) vhdl semantics (estimated time: 15 minutes) For the vhdl program below, calculate the values for the signals a1, b1, c1, a2, b2, and c2 at. <= to_unsigned( 7, 4 ); wait until rising_edge(clk1); <= to_unsigned( 8, 4 ); wait until rising_edge(clk1); <= to_unsigned( 9, 4 ); wait until rising_edge(clk1); end process; 10ns+3 clk1 clk2 a b c a1 b1 c1 a2 b2 c2. No changes from end of 10ns + 3 simulation cycle to 15 ns. Q2 (20 marks) data ow diagram and control table (estimated time: 15 minutes) In this question you will do register allocation and draw the control-table for the data ow diagram shown below. Notes: the optimization goal is to minimize the total number of multiplexers and chip-enables.