jameshall

The following algorithm is used to find the integer square root for an input integer number � [ Ex1: if xin{4,5,6,7,8}, then the result integer square root �=2 ] [ Ex2: if xin{9,10,11,12,13,14,15}, then the result integer square root �=3 ] Input: �, ( �-bit integer number) Output: �=� Step1: Initialization �=� (Input Data) �=1 �=3 step2: �=�+� step3: �=�+2 repeat the last two steps (step 2 and step 3) until Q > A step4: Shift B one bit to the right (a logical shift) step5: �=�-1 (The result) Complete the following Verilog code to provide a behavioral implementation for this algorithm. module SQRT_Calculator ( input CLK, input [9:0]�, output reg [4:0] � ; Your design should include the following pins: CLK: (negative edge trigger input clock) � : The input number (10 bits) �: The result square root ( 5 bits) (Hint: define the variables A, B, and � to be of size 11) Notes: Use behavioral description DO NOT use the following operators: /,**,% DO NOT use an algorithmic state machine. The calculation should be synchronous with the clock (the result should be calculated in a single clock cycle at the falling edge of the input clock) You have to use EDA Playground for this assignment You have to submit two files: A Verilog code to implement your Design. A testbench file to simulate and test your design: a. Set the clock period to be 2��. b. You have to cover all the possible cases for the input data (1024 different cases) c. For each case you have to: i. Select the value for � (from 0 to 1023) ii. Wait for two clock cycles