MAT2006 Chapter Notes -The Terminal, Leading Edge, Txe
10 Apr 2023
Department
Course
Professor
Document Summary
This is bidirectional data bus which receive control words and transmits data from the cpu and sends status words and received data to cpu. A "high" on this input forces the 8251 into "reset status. " The device waits for the writing of "mode instruction. " The min. reset width is six clock inputs during the operating status of clk. Clk signal is used to generate internal device timing. Clk signal is independent of rxc or txc. However, the frequency of clk must be greater than 30 times the rxc and txc at synchronous mode and asynchronous. "x1" mode, and must be greater than 5 times at asynchronous "x16" and "x64" mode. This is the "active low" input terminal which receives a signal for writing transmit data and control words from the cpu into the 8251. This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
