EE 101A Midterm: EE 121 Midterm 1

• School: Stanford University
• Department: Electrical Engineering
• Course: EE 101A
• Professor: all

Document Summary

Time limit: 75 minutes: (20 points) cmos logic circuit. Write the truth table and a logic diagram for the logic function performed by the following cmos circuit. A logic designer with time on his hands connected a 74x138 decoder and a 74x148 priority encoder as shown below. In this problem, we consider the even more reliable quadruple modular redundancy. Write optimized boolean equations (minimal sums of products) for each of the outputs of the qmr circuit. Your equations for y should be simpli ed by using the fact that the value of y does not matter when fail is true. The combinational logic propagation delays for the component shown below are di erent for the four outputs, as shown in the following table. Y4: suppose that the propagation delay of an xor gate is 10 ns. Propagation delay (xor delay 10 ns): suppose that the propagation delay of an xor gate is 30 ns.