CS230 Study Guide - Final Guide: Static Random-Access Memory, Complex Instruction Set Computing, Memory Hierarchy

• School: University of Waterloo
• Department: Computer Science
• Course: CS230
• Professor: Sandy Graham

Document Summary

2d matrix via memory bus: cpu sends address to memory controller, controller responds with data. Stable storage, as long as power is applied single transistor per bit. Same data item likely to be used again soon. Close data item likely to be used soon e. g. , loop e. g. , iteration through array. Everything else as a cache, different perspectives exist. Satisfy as many requests as fast as possible. Register > cache > main memory > disk > network > off- site archive/tape/optical. Caching small amount of fast memory: keep recently used (and nearby) data in cache, keep after use or, limited fast memory: replacement strategy, shared remote data: prefetch invalidation. Direct mapping cache, cache entires and block size: Assume m blocks of cache memory with size b. Many memory blocks map to same cache block. Larger blocks reduce miss rate due to spatial locality. Request for address p add tags to identify which one is present.