CSCE 3613 Lecture Notes - Lecture 2: Interrupt Vector Table, Direct Memory Access, Institute For Operations Research And The Management Sciences
24 Aug 2016
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Document Summary
Computer startup: bootstrap program is loaded at power-up or reboot. Typically stored in rom or eprom, generally known as firmware. One or more cpus, device controllers connect through common bus providing access to shared memory. Concurrent execution of cpus and devices competing for memory cycles. I/o devices and the cpu can execute concurrently. Each device controller is in charge of a particular device type. Cpu moves data from/to main memory to/from local buffers. I/o is from the device to local buffer of controller. Device controller informs cpu that it has finished its operation by causing an interrupt. Transfer control to interrupt service routine, trhough interrupt vector, contains addresses of service routines. Architecture must save the address of interrupted instruction. Incoming interrupts are disabled while another interrupt is being processed. After i/o starts, control returns to user program only upon i/o completion. Wait instruction idles the cpu until next interrupt. At most one i/o request is outstanding at a time.
