CS 25000 Lecture Notes - Lecture 15: Propagation Delay, Instruction-Level Parallelism, Opcode
20 Mar 2017
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Pipelined design: change one-instruction-per-clock cycle design to one-instruction-stage-per-clock cycle, overlap as many instructions as there are stages, ideally, complete all stages every clock cycle, ideally. Control of the data path: control unit generates all control signals. Branch if equal: fetch instruction, read source registers, compare and by subtracting them in the alu. Is result is 0, then source operands were equal and pc should be loaded with target address: else the branch shouldn"t be taken and pc pc + 4 to fetch the next sequential instruction. Use current_pc to address instruction memory and compute. Decode instruction fields, read registers to obtain operands, and send opcode field to input of boolean control logic circuit to generate all control signals. Read or write data memory, if required, using the address computed by the alu. Write the result from ex or mem, if there is a result, into the destination register.
