CSCI 2400 Lecture Notes - Lecture 11: Synchronous Dynamic Random-Access Memory, Static Random-Access Memory, Ddr3 Sdram
6 Apr 2019
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Document Summary
Ram is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell) Basic dram cell has not changed since its invention in 1966. Dram cores with better interface logic faster i/o: Uses a conventional clock signal instead of asynchronous control. Allow reuse of the row addresses (ex: ras, cas, cas, xas) Double edge clocking sends two bits per cycle per pin. Different types distinguished by size of small prefetch buffer: Ddr (2 bits), ddr2 (4 bits), ddr3 (8 bits) By 2010, standard for most server and desktop system. Intel core i7 supports ddr3 and ddr4 sdram. Nonvolatile memories retain value even if powered off. Programmable rom (prom): can be programmed once. Erasable prom (eprom): can be bulk erased (uv, x-ray) Flash memory: eeproms, with partial (block-level) erase capability. 3d point (intel optane) & emerging nvms. Firmware programs stored in a rom (bios, controllers fro disks, network cards, graphics accelerators, security subsystems, )
