ENVS 1000 Lecture Notes - Lecture 3: X86, Execution Unit, Itanium
10 May 2018
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ENVS 1000 Tutorial 3 Notes – Separate fetch unit/execute unit
Introduction
• The model provides separate execution units for different types of instructions.
• This makes it possible to separate instructions with different numbers of execution
steps for more efficient processing.
• It also allows the parallel execution of unrelated instructions by directing each
instruction to its own execution unit.
• You have already seen this method applied to the Transmeta and Itanium architectures
• We next consider each of these techniques in turn.
• Picture a modified Little Man Computer in which the Little Man has been given an
assistant.
• The assistant will fetch and decode the instructions from the mailboxes at a pace that
allows the Little Man to spend his time executing instructions, one after another.
• Note that a similar division of labor is used in a restaurant
• Waiters and waitresses gather the food orders from the customers and pass them to the
cooks for processing.
• The current preferred CPU implementation model divides the CPU similarly into two
units, which correspond roughly to the fetch and execute parts of the instruction cycle.
• To achieve maximum performance, these two parts operate as independently from each
other as possible, recognizing, of course, that an instruction must be fetched before it
can be decoded and executed.
• This alternative CPU organization.
• The fetch unit portion of the CPU consists of an instruction fetch unit and an instruction
decode unit.
• Instructions are fetched from memory by the fetch unit, based on the current address
stored in an instruction pointer (IP) register.
• The fetch unit is designed to fetch several instructions at a time in parallel.
• The IP register effectively acts as a program counter.
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