CSC258H1 Lecture Notes - Memory Buffer Register, Memory Address, Readwrite
Document Summary
Reading and writing of signals to and from memory is expensive. In this example there is a 75ns write cycle between the start of the write process and the point at which the write process is complete. 6 address bits 26 lines of memory. Total: 64 lines of memory (memory slots) 32-bit architecture 4 bytes per memory address. Ram capacity = 64*6 = 256 bytes of memory: q2: Interval 1 = setup address time for the address to be written at to be available for writing. Interval 2 = setup data time for the data values to written at the address. To signal done writing, make sure address stop writing well before data becomes invalid/unavailable. Address acces time (taa) time needed for address values to be stable before reading data values (~10ns)
