CEG 3136 Lecture Notes - Lecture 8: Interrupt Handler, Asynchronous Circuit, Subroutine

• School: University of Ottawa
• Department: Computer Engineering
• Course: CEG 3136
• Professor: Basim Hafidh

Document Summary

Internal asynchronous cpu timing: interrupts can occur at any time during an instruction cycle, at the next instruction cycle that"s when it will check if there"s be an interrupt. Internal cpu interrupt hardware: use a flip-flop (irq-ff) to catch irq. Interrupt-vector table: practical in microcontrollers, all peripheral devices in a microcontroller invokes separate irq signals, enabling interrupts from multiple sources, interrupt masking. Interrupt latency: time between interrupt assertion and start of service routine. Which includes: completion of current instruction, time to save registers on the stack, resolve priorities, and completion of other service routines. Irq pin (port e: peripheral modules, port p: 8 pins, port j: 2 pins, non-maskable, xirq pin, swi, and illegal opcode trap, reset: power on, manual reset, cop (computer operate properly), and. Internal interrupts: external interrupts (irq, xirq, port p, port j, rising edge triggered (irq, xirq, port p & port j) or falling. If no other interrupt is pending, restore pc.