CPSC 313 Lecture Notes - Lecture 6: Cache Coherence, Mesi Protocol, Memory Address
5 Jun 2016
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Cache coherence: all valid cache line corresponding to a given memory address must agree on the value. Rst write op writes to main memory other cores" caches invalidate their copy of the cache block. A: the value might change repeatedly, keeping all copies up to date takes too much bandwidth subsequent write operations only update the cache. Each cache block is one of four states: Cache performance is workload dependent access traces are run to count the hits and misses (simulate cache behaviour) Things to measure: hit rate hit time miss rate and penalty for each type of miss.
