CPSC 313 Lecture 3: [10/26] Cache Memory Organization
5 Jun 2016
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A valid bit (1 if valid, 0 if invalid) tage used to determine right data multiple data blocks may end up in the same location. Data will end up in the same place in the cache if they have the same tagline. To nd an item in the cache: find the cache index & read the cache line at that index, check for valid bit (is 1?, compare tags. They may be the same set of bits for a loooooooong time (if the data involved are close to each other) Dmc tends to give you more misses in the cache. Fully associative caches: block"s address does not determine which cache line it is stored in we can place the block anywhere in the cache. But: eviction becomes more complicated locating data is more complex takes more circuitry and is slower (increases clock cycle)
