COMPENG 2DI4 Lecture Notes - Lecture 21: Sequential Circuits, Eprom, State Diagram
12 Feb 2015
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Midterm descriptive stats: multiple choice - mean 72, short answer - mean 49% (n=220, exam average* - mean 60, bonus average - 72% (n=83) Based upon average of mc and sa - exact value yet to be calculated. Lab 04: midterm break, oct. 30 lab is moved to nov. 6 2:30-5:30, oct. 31 lab is moved to nov. 6 5:30-8:30, content, synchronous sequential circuits (physical and hdl, accessing digital memory (eprom) as a lut. Lab 05: implementation of function generator using hdl, Eprom, and operational ampli er (opamp: synthesis and implementation of synchronous sequential logic circuit. Lab 06: practical lab, 50 minutes, performed individually, assigned at a time during normal lab session. Cscs sequential circuits (cscs): we have completed the analysis of clocked, now look at synthesis of clocked sequential circuits, begin with a speci cation and translate into a digital logic form. In nite number of inputs are possible, thus in nite outputs from circuit.
