I&C SCI 51 Chapter Notes - Chapter 4: Memory Buffer Register, Memory Address Register, Instruction Set

• School: UC-Irvine
• Department: Information and Computer Science
• Course: I&C SCI 51
• Professor: Shannon Alfaro

Document Summary

Ics 51 notes chapter 4. 1 (an example microarchitecture) Contains micro program (in rom), job is to fetch, decode and execute ijvm instructions. Each instruction at isa level is a function to be called by master program. Master program simple endless loop, determines function to be invoked, calls it, then starts over. Variables state of computer, accessed by all functions. First field is opcode, identifies the instruction (ex. Additional field is the operand field (access local variable, this field tells it which variable) Data path part of cpu containing alu, its inputs, and its outputs. Delta w control signals are set up. Delta x - registers are loaded onto the b bus. Delta z results propagate along the c bus back to the registers. The memory address register and memory data register. Each driven by one or two control signals, read or write signal is issued to memory after register is loaded. Mar contains word addresses; pc contains byte addresses.