MGMT 1050 Chapter Notes - Chapter 16: Instruction Set
MGMT 1050 Chapter 16 Notes – Summary
Introduction
• Some of the enhancements that were introduced include direct support for floating
point arithmetic, BCD arithmetic, and multimedia processing
• As well as the inclusion of additional addressing modes, which simplify data access,
increase potential memory size capability while maintaining reasonable instruction word
sizes, and improve list and array processing.
• We have already presented a number of architectural enhancements that can improve
performance including features.
• Allow parallel execution of instructions to improve processing speed, register-oriented
instructions, the use of fixed-width instructions, and integral code-morphing software.
• Since the purpose of a computer is to execute programs, the ability of the CPU to
execute instructions quickly is an important contributor to performance.
• Once a particular architecture is established, there remain a number of different ways to
increase the instruction execution performance of a computer.
• One method is to provide a number of CPUs in the computer rather than just one.
• Since a single CPU can process only one instruction at a time, each additional CPU
would.
• In theory, multiply the performance of the computer by the number of CPUs included.
• We will return to a discussion of this technique later.
• Of more interest at the moment are approaches that can be used to improve the
performance of an individual CPU.
• In our introduction to CPU architectures, we suggested a number of possibilities.
• Some of these require new design, such as the large number of registers and register-to-
register instructions that are characteristic of newer architectures.
• As we already noted, even with older instruction sets, it is often possible to use code
morphing to create an intermediate instruction set that is used within the CPU as a
substitute for the more complex, original instruction set.
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