MGMT 1050 Chapter Notes - Chapter 14: Transmeta Efficeon, Very Long Instruction Word, Instruction Set
MGMT 1050 Chapter 14 Notes – Summary
Introduction
• It is permanently resident in memory and processes every instruction prior to execution.
• In addition to instruction translation, the code-morphing layer also reorders the
instructions as necessary to eliminate data dependencies and other bottlenecks.
• Although this sounds like an inefficient way to process instructions, Transmeta has
demonstrated that the simplicity of its VLIW design.
• The sophistication of its code-morphing software allow execution of the Pentium
instruction set at speeds comparable to the native execution speeds of a Pentium
processor.
• Transmeta claims, with apparent justification, that this simplicity allows a much simpler
CPU design, with fewer transistors and much lower power consumption.
• Resulting from the elimination of complicated hardware implementation features
commonly used to achieve high execution speeds in a conventional CPU design.
• The Efficeon CPU extends the Crusoe architecture to 256 bits, representing eight 32-bit
atoms to be executed simultaneously.
• At present, Transmeta has provided a code-morphing layer only for the Pentium CPU
family.
• However, if there were reason to do so, Transmeta could easily create code-morphing
layers for other CPUs.
• The EPIC architecture, designed by Intel for its IA-64 processor family, attempts to
achieve similar goals by slightly different means.
• The basic instruction set architecture is new, although Intel has built x86 capability into
the CPU to support compatibility with its earlier architecture.
• The IA-64 offers 128 64-bit general-purpose registers and 128 82-bit floating point
registers.
• All instructions are 41 bits wide.
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