FIT1047 Chapter Notes - Chapter -: Binary Number, Hard Disk Drive, Gibibyte
31 May 2018
School
Department
Course
Professor
MARIE
Monday, 19 March 2018
4:00 PM
Data Paths
The data paths in a CPU describe how the different functional units, in particular the registers and
the ALU, are connected. The hardware implementation of the data paths in the system bus (or
simply bus), the set of "wires" in the CPU that connects all the components.
In Marie:
The blue data bus can transport individual words of data between the memory, the registers and the
ALU.
The only way to get data from memory into a register, or from register into memory is via the
memory buffer register MBR.
Ex. For an instruction like Load 005, the CPU cannot directly transfer the value at address 005
into the AC register, it has to first load it from the memory into the MBR and then from there
into the AC.
The green address bus connects the memory with the MAR (memory address register). It is
responsible for selecting the memory address that the CPU reads from or writes to.
Ex. Load 005 --> CPU has to put the value 005 into MAR, which tells the memory to "activate"
address 005.
The red control bus doesn't transport addresses or data words. It is used by the Control Unit (CU) to
selection different modes of operation on the other components.
Ex. It is not enough for the memory to know that the address it should use it 005. It also needs
to know whether is should transfer the current contents of 005 into the MBR (as for a Load
instruction), or rather go in the opposite direction and transfer the current data word from
MBR into address 005.
• The control unit can therefore switch the memory from "read mode" into "write mode," and
hat switch one of the signals on the control bus.
• The CU also needs to be able to tell the ALU which operation to perform (ex. Whether to add
or subtract) This is also done via the control bus
• The CU needs to select which register to read from and write to.
o Ex. In a Jump 102 instruction it would have to write the value 102 into the PC register,
but in many other instructions, it has to read from or write to the AC register.
The IR and PC registers are used by the CU to keep track of which part of our program is currently
executing. The IR contains the currently executing instruction, while the PC contains the address of
the next instruction to be executed after the current one has finished.
Register Transfer Language
The fetch-decode-execute cycle defines a sequence of even lower-level steps that each instruction
can be broken down into.
Fetch
The PC register contains the address of the next instruction that needs to be executed. The control
unit needs to load the next instruction from the memory address stored in PC into the IR register,
and then increment the PC register, so that it points to the next instruction again.
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Loading from memory means the address must be put into the MAR, and the result will then
be transferred into the MBR - but we need the result in the IR, so we need another transfer
from the MBR to the IR.
This means that even for the fetch stage of each instruction, the CPU already does four small steps.
1. MAR <-- PC
2. MBR <--- M[MAR]
3. IR <---- MBR
4. PC <-- PC + 1
The first steps copies the address stored in the PC into the MAR.
The next step reads the memory location MAR (written as M[MAR]) into MBR.
The third step copies the contents of MBR into the IR.
Now the instruction that is stored at the address in PC has been fetched into the instruction register
IR.
The final step increments the PC.
Noe how we can write simple arithmetic expressions on the right hand side, which will have to be
performed by the ALU.
Decode
This is where the control unit looks at the instruction in the IR and figures out what needs to happen.
Most instructions contain an address x, and since we have a special register for handling addresses
(the MAR), the first step in the decode phase is to put x into MAR.
5. MAR <--- X
If the instruction needs to read any data from memory, then that is also done in the decode phase.
In the case of MARIE, the instructions that read from memory are Load X, Add X, Subt X, and all
indirect addressing instructions. For these instructions, the final step of the decode phase is
therefore to read the data word from memory into the memory buffer register MBR:
6. MBR <---- M[MAR]
Execute
This phase, naturally depends on the actual instruction being executed.
Most common instructions:
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Document Summary
The data paths in a cpu describe how the different functional units, in particular the registers and the alu, are connected. The hardware implementation of the data paths in the system bus (or simply bus), the set of wires in the cpu that connects all the components. The blue data bus can transport individual words of data between the memory, the registers and the. The only way to get data from memory into a register, or from register into memory is via the memory buffer register mbr. For an instruction like load 005, the cpu cannot directly transfer the value at address 005 into the ac register, it has to first load it from the memory into the mbr and then from there into the ac. The green address bus connects the memory with the mar (memory address register). It is responsible for selecting the memory address that the cpu reads from or writes to.
