ELEG 4983 Lecture Notes - Lecture 2: Speedup

• School: University of Arkansas
• Department: Electrical Engineering
• Course: ELEG 4983
• Professor: David Andrews

Document Summary

Speed up was thought to have been able to be at least with a slope of 1 linear but in actuality it was less and non-linear. If f = fraction of code that can be parallelized then. Speed up is extremely limited by fraction of sequential code. Example: two alternatives of being able to speed up code available. Need to know which speed up is greater. Alt 1: speed up floating point multiplication by 10x. Alt 2: speed up all floating point operations by 2x. Need to know percentages of code that are floating point multiply (fpm) and floating point (fp) If 5 % fpm and 20 % fp. We need risc scalar cpu to input 1 instruction per clock cycle. Cpu will need to fetch each instruction from dram. Must also wait 40/. 4 = 100 clocks between accesses due to cycle time. Cpu is pin limited and cannot simultaneous instruction fetch.