ESE 345 Lecture Notes - Lecture 14: Memory Address, Clock Rate, Datapath
27 Dec 2020
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Document Summary
Mem: read/write the data from/to the data memory. Wb: write the result data into the register file. Start the next instruction while still working on the current one. Improve throughput or bandwidth: the total amount of work done in a given time (average instructions per second or per clock) Instruction latency is not reduced (time from the start of an instruction to its completion) Pipeline clock cycle (pipeline stage time) is limited by the slowest stage. For some instructions, some stages are not used/wasted cycles. Latency per lw = 5 clock cycles for both. Bandwidth of lw is 1 instruction per clock (ipc) for pipeline vs ipc for a multicycle processor. Pipelining improves instruction bandwidth, not instruction latency. All instructions are the same length (32 bits) Easier to fetch in 1st stage and decode in 2nd stage. Few instruction formats (three) with symmetry across formats. Can begin reading register file in 2nd stage.
