ESE 345 Lecture Notes - Lecture 16: Intrinsity, Cache Memory, Cache Replacement Policies
27 Dec 2020
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Document Summary
Generally implemented directly as a register file. Address usually computer from values in register. Generally implemented as a hardware-managed cache hierarchy. Hardware decides what is kept in fast memory. But software may provide hints, i. e don"t cache or prefetch. Hit: data appears in some block in the upper level (example: block x) Hit rate: the fraction of memory access found in the upper level. Hit time: time to access the upper level which consists of ram access time + Miss: data needs to be retrieve from a block in the lower body (block y) Miss rate = 1 - (hit rate) Miss penalty: time to replace a block in the upper level + time to deliver the block the processor. Temporal locality: if a location is referenced it is likely to be referenced again in the near future. Spatial locality: if a location is referenced it is likely that locations near it will be referenced in the near future.
