Electrical and Computer Engineering 2277A/B Lecture Notes - Lecture 42: Clock Signal, Propagation Delay
24 Jan 2021
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Ripple counter: some flip flops triggered by outputs from other flip flops. Ripple counters are designed and analyzed using ad hoc methods. In this type of structure, each flip-flop is trigger by a different but related clock signal. The relationships is that the clock of the ( )th flip-flop is the output of the th flip-flop. Extracting the input equations is not quite the same as we"ve seen previously. We must examine the state evolution carefully to see signal flow in this structure. Propagation delay for toggling th bit = flip-flop propagation delay. Typical msi flip-flop chip maximum propagation delay 40 ns. Binary ripple counters require no logic gates external to the flip flops. A binary ripple counter is slower than a synchronous binary counter, but the ripple counter"s cost is lower. Transition of less-significant digit from 1001bcd to 0000bcd provides negative-edge trigger to counter for next-more-significant digit. Binary ripple counters can be combined in the same fashion.
