Electrical and Computer Engineering 2277A/B Lecture Notes - Lecture 24: Xor Gate, Or Gate, Propagation Delay
20 Jan 2021
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Document Summary
A ripple adder consists of cascaded full adders. Adds two 4-bit numbers, and , and an incoming carry bit, c0. 9 inputs, so complete truth table has 29 = 512 rows. Assuming , , and c0 are updated simultaneously, outgoing carry bit, c4, does not update until carry results propagate through all 4 full adders. Assuming , , and 0 are updated simultaneously: 1 will update after xor gate delay + and gate delay + or gate delay. For = 1 to 3, i+1 will update 2 gate delays (and and or) after i. For -bit adder, delay from updating 0 to updating n is = Xor delay + n (and delay) + n (or delay) Worst-case total delay for 8-bit adder = 30 ns + 8 (27 ns) + 8 (22 ns) = 422 ns. Th carry generate bit, i = th sum bit = i = i i ( )th carry bit = i+1 = i i i.
